From AMD’s internal display, more precisely “Update the design status for EPYC“, is said to be a roadmap providing information about the upcoming Zen 5 and Zen 6 architectures. There is also a diagram of the Nirvana (Zen 5) architecture.
It is not possible to determine the authenticity or age of the presentation slides on the YouTube channel Moore’s Law is dead He posted it and, according to his own statements, changed it visually to protect the source. Therefore, the information should be treated with caution.
Since looking at the profile of an AMD employee on LinkedIn, it has become known that the microarchitecture of Zen 5 is codenamed Nirvana, while its successor is Morpheus (Zen 6).
Information about Zen 5 architecture (Nirvana)
According to the roadmap, Nirvana is targeting an increase in instructions per clock cycle (IPC) in the range of 10 to 15 percent. Based on the previous, albeit equally uncertain, Cinebench benchmark, the channel assumes a larger increase. At least the IPC should increase to a greater extent than when switching from Zen 3 to Zen 4 by 14 percent (according to the roadmap). However, IPC information is generally difficult because it always ultimately depends on the viewing angle or application.
While Zen 4 was just an update of Zen 3 with relatively small changes, Zen 5 is said to be an entirely new microarchitecture, as AMD itself has said.
If the information in the roadmap is correct, a lot will change. The L1 data cache will be increased from 32KB to 48KB and counting ALUs It should increase from 4 to 6 and thus also by 50 percent. However, the L2 cache remains unchanged at 1MB per core.
Furthermore, there are variants of FP-512 and “A basic, low-energy option” speech. Zen 5 will now have up to 16 active cores per Core Complex (CCX), which is twice the number compared to Zen 4. In this context, it is unlikely that the smaller “c” cores are meant here, as is the case. In Zen 4c (Bergamo, Siena), because this option already existed in the predecessor and therefore would not be “new”.
However, the roadmap may not be up to date at this point, so the Zen 4c and 16-core CCX meaning Zen 5c have been omitted. In the upcoming Strix Point series APUs, AMD is expected to combine full Zen 5 cores with smaller Zen 5c cores.
Moore’s Law is dead (MLID) also assumes that, like its predecessor, there will be a CCX with 8 large cores and a CCX with 16 small “c” cores.
The channel had previously published another roadmap containing equally unconfirmed data about AMD’s upcoming server processors. There is talk of up to 128 Zen 5 cores in Turin, the successor to Genoa, and 192 Zen 5c cores in “Turin Dense”, the successor to Bergamo.
Information about Zen 6 (Morpheus)
There should only be a small jump from Zen 5 to Zen 6 (codename Morpheus). A very early, and therefore rough, forecast is that the IPC will rise by at least 10 percent. In addition, the 32-core CCX was mentioned for the first time. There’s also talk of memory profiling and FP16 commands for AI and machine learning.
For Zen 6, MLID expects a new design with new packaging technologies and a new generation of Infinity Fabric. The channel is not yet sure that the CPU chips (CCD) will be stacked directly on the input/output die (IOD).
Zen 5 is expected to debut in the first half of 2024 and Zen 6 in the second half of 2025.
“Subtly charming coffee scholar. General zombie junkie. Introvert. Alcohol nerd. Travel lover. Twitter specialist. Freelance student.”